Silicon capacitor adoption arbitrages package economics invisible to component analysts
gen-silicon-capacitor · conviction — · status open · horizon — · as of 2026-08-10
silicon-capacitor.capex_pull>=14.6012 — 8.438 to 19.78silicon-capacitor.demand_pull>=58.58 — 41.41 to 58.07How to read the numbers on this page
A range instead of a point. 903 of 1,848 supply weights are not disclosed by anyone. Where redrawing them across their plausible range moves a figure by more than 25%, the figure is shown as a range and marked. A tight number is ground you can stand on; a wide one is not.
Not every premise is scored. A premise citing something the model verifies on every rebuild — a filed figure, a graph edge, a computed cell — is a PRECONDITION, not a risk. It gates the conclusion but contributes no uncertainty, because charging a conclusion for being verifiable made well-evidenced arguments look weaker than vague ones.
Composed two ways. Where several premises gate a conclusion, the figure is given as "X% if independent, Y% if they move together". They are claims about one industry, so the truth is between and nobody can say where. Treat it as an ordering device, not a calibrated probability.
Dated. Each figure is computed from facts, and the page states the age of the oldest one beneath it. The full arithmetic runs from a published model config to company revenue exposure.
Exhibits
Series available as data/gen-silicon-capacitor.csv
The variant
Consensus
Silicon capacitors are a niche power-integrity solution for high-performance AI accelerators, beneficial where it matters but unlikely to reshape packaging economics. Demand scales with datacenter AI buildout. The technology remains incremental—a helper part—rather than a strategic shift, tracked primarily by passive-component specialists rather than packaging or semiconductor equity desks.
Variant
Silicon capacitor adoption is determined by the customer's willingness to convert operating margin into package capex, not by absolute accelerator demand. Intel, AMD and NVIDIA face radically different margin structures: NVIDIA at 64% operating margin can absorb in-package solutions that Intel at -23% cannot economically justify despite identical power-delivery physics. The technology's attach rate will bifurcate by customer profitability, not by node or workload, creating durable volume concentration at the hyperscale leaders—a margin arbitrage dynamic that component-coverage models miss entirely because they model demand as a pure function of AI unit growth.
Differentiator
Component analysts model silicon capacitors as a feature driven by technical need (power delivery, transient response). The supply chain reveals it as a *margin tax*: only customers converting rent into advanced packaging can afford in-package decoupling at scale. Customer operating margins span 87 percentage points; capex intensity follows that divergence, not the AI growth rate.
Falsifiers
- claim: Silicon capacitor attach rates stratify by customer operating margin · criterion: Intel's silicon capacitor procurement as % of packaging spend falls below AMD's despite similar or higher accelerator SKU count by 2027 roadmaps · horizon: 2027-06-30 · settles: confirmed
- claim: Powerchip exclusivity with Intel is a concentration risk, not a moat · criterion: Powerchip discloses Intel revenue <40% of silicon capacitor segment revenue, or Intel cuts EMIB-T volume guidance · horizon: 2027-03-31 · settles: confirmed
- claim: Component analysts will misallocate silicon capacitor TAM by customer · criterion: NVIDIA's disclosed or supplier-attributed silicon capacitor spend per accelerator exceeds Intel's by >2.5x in calendar 2027 despite Intel's public roadmap naming the technology · horizon: 2028-02-28 · settles: confirmed
Open questions
- What is the $/mm² cost delta between in-package silicon capacitors and board-level MLCC arrays at equivalent decoupling performance? If silicon is <1.3x the MLCC cost, margin arbitrage dominates; if >2x, even NVIDIA may gate adoption.
- Does Powerchip's Intel exclusivity cover *all* deep-trench capacitor architectures or only the specific EMIB-T integration? A narrow scope lets Intel diversify; a broad one locks both parties into a fragile dependency.
- How does AMD's 11.8% operating margin position it relative to Intel and NVIDIA on packaging investment? MI300's multi-chiplet design suggests high decoupling need, but margin is closer to Intel's constraint than NVIDIA's freedom.
Reasoning chain
NVIDIA Corporation — operating margin 64.0%1.00 strongFiled, verified.why
Establishes the profit cushion available for packaging spend.
Intel Corporation — operating margin -23.1%1.00 strongFiled, verified.why
Negative margin leaves no room for incremental package cost.
Silicon capacitor (in-package decoupling) — capex pull at least 14.6012 [8.44–19.8 depending on shares nobody discloses]1.00 strongCustomer-weighted capex intensity already computed and bounded by supply chain.Package shoreline (perimeter and cross-section contention between power, memory and data)0.75 strongAssumes perimeter contention remains binding enough to push decoupling on-package rather than solved by board-level design or voltage architecture changes.Silicon capacitor (in-package decoupling) supplies NVIDIA Corporation1.00 strongAssumes NVIDIA adopts silicon capacitors in volume production; edge existence does not confirm attach rate or commercial terms.Silicon capacitor (in-package decoupling) supplies Intel Corporation1.00 strongIntel named Powerchip exclusively for EMIB-T, but whether loss-making business sustains premium packaging components at scale is unverified.
Composed 0.75 via and over 3 gating premises · 3 supporting premises shown but not multiplied in — citing a filed figure should not cost conviction · Weakest link Package shoreline (perimeter and cross-section contention between power, memory and data) at 0.75
14.6% capex pull against 87pp margin spread implies packaging investment decisions decouple from technical roadmap alignment and follow financial capacity instead.
Powerchip Semiconductor Manufacturing (PSMC) supplies Silicon capacitor (in-package decoupling)1.00 strongRecorded edge, validated.why
Confirms Powerchip supplies this category.
Powerchip Semiconductor Manufacturing (PSMC)0.70 moderateAssumes exclusivity is platform-locked, not technology-locked; if Intel pivots or cuts advanced packaging spend, award evaporates.Intel Corporation — operating margin -23.1%1.00 strongFiled.why
Customer in structural loss limits ability to ramp premium packaging components.
Intel Corporation0.65 moderateIntel's packaging roadmap execution and margin recovery timeline remain uncertain; exclusivity with a restructuring customer is fragile.
Composed 0.45 via and over 2 gating premises · 2 supporting premises shown but not multiplied in — citing a filed figure should not cost conviction · Weakest link Intel Corporation at 0.65
Single-source status with a negative-margin customer inverts the usual moat logic: concentration becomes a liability if Intel cannot fund the roadmap.
Silicon capacitor (in-package decoupling) — demand pull at least 58.58 [41.4–58.1 depending on shares nobody discloses]1.00 strongCustomer-weighted growth already computed.why
Establishes the blended demand signal analysts see.
NVIDIA Corporation — revenue growth $851.00 strong12xFiled.why
NVIDIA growth is 12x Intel's, and operating margin permits packaging investment Intel cannot match.
Datacenter Ai0.80 strongAssumes datacenter AI growth continues to drive accelerator complexity; a plateau or shift to inference-optimized designs would reduce decoupling need.Silicon capacitor (in-package decoupling) supplies NVIDIA Corporation1.00 strongSame as above: edge exists but attach-rate ramp and commercial volume unconfirmed.
Composed 0.80 via and over 1 gating premise · 3 supporting premises shown but not multiplied in — citing a filed figure should not cost conviction · Weakest link Datacenter Ai at 0.80
58.6% demand pull reflects customer revenue growth, but margin divergence means NVIDIA will convert growth into packaging adoption while Intel cannot—a split invisible in unit-based TAM models.
Sources
- Value-chain role and CUDA moat characterization — link acc 2026-07-21
- Q1 FY2027 (ended 2026-04-26) revenue $81.6B, up 85% YoY, GAAP gross margin 74.9% — link acc 2026-07-21
- TTM revenue $253.49B, gross margin 74.15%, operating margin 64.02%, market cap $5.03T, forward P/E 20.42, TTM capex $6.57B — link acc 2026-07-21
- Market cap ~$673B (June 2026) — link acc 2026-07-21
- Forward P/E — link acc 2026-07-21
- Net cash -$11.93B i.e. net debt (site headline; components $17,247M cash + $15,542M ST investments minus $2,004M ST + $43,027M LT debt give -$12.24B), TTM FCF -$3.119B, TTM buybacks and dividends both zero — all TTM thro — link acc 2026-07-22
- suppliers weights (ESTIMATED except tsmc). tsmc@1.0 = sole leading-edge foundry (structural single-source, mirrors manufactures_at@1.0). HBM sourced across three vendors; NVIDIA's HBM4 allocation reported ~SK hynix mid-5 — link acc 2026-07-21
- uses_technology weights (STRUCTURAL/qualitative). CoWoS advanced packaging and HBM3E are single-source hard dependencies gating accelerator output → cowos@0.9, hbm3e@0.9; tsmc-3nm leading-edge node is likewise a hard dep — link acc 2026-07-21
Write-up
Pre-filled skeleton: gen-silicon-capacitor.md