The China chokepoint moves from lithography to bonding — and the substitution trade is priced in the wrong category

bonding-not-litho · conviction medium · status open · horizon 2026-2028 (DF2000 Q4-2026 is the first dated test) · as of 2026-08-03

Export controls are read as a lithography constraint, and the domestic-substitution trade is priced accordingly in etch and deposition where NAURA and AMEC already hold share. If China's answer is to go VERTICAL rather than smaller — 3D stacking, wafer-to-wafer hybrid bonding, memory fused onto logic — the binding constraint stops being litho and becomes bonders and sub-0.5um overlay metrology, a category where domestic share is near zero and the incumbents are BESI, ASMPT, EVG, SUSS and Applied.

Rests on shares nobody discloses. 1 of 1 derived inputs move materially when the undisclosed supply weights are redrawn across their plausible range. The argument may still hold — but these figures are ranges, not points. Computed from evidence at most 17 days old (oldest input: amd).

hybrid-bonding.demand_pull — 48.02 to 73.26

Exhibits

Exhibit 1Relative performance, indexed to 100How the names in this thesis have traded against SOXX.

Series available as data/bonding-not-litho.csv

Exhibit 2What the conviction is actually made ofEach premise and the number it composes to. A conjunction of plausible premises is far weaker than any of them.

The physical mechanism is real and vendor-independent: perimeter-bound resources cannot keep pace with area-scaled compute, so pac

86% if the 3 gates are independent, 90% if they move together. They are claims about one industry, so the truth is between and nobody can say where. Treat this as an ordering device rather than a calibrated probability — the ranking of premises is the information, not the level.

Weakest link: Perimeter-vs-area scaling gap (the N-squared vs N fan-out dilemma) at 0.90 — Asserted by Huawei, which needs litho-independent scaling to be true, AND demonstrated by NVIDIA's shipping roadmap, which has no such incentive. Conv

China's vertical escape is now constrained at the SAME chokepoint this thesis identified, as of 2026-08-01

60% if the 2 gates are independent, 75% if they move together. They are claims about one industry, so the truth is between and nobody can say where. Treat this as an ordering device rather than a calibrated probability — the ranking of premises is the information, not the level.

Weakest link: Chinese domestic share of wafer-to-wafer hybrid bonders at 0.75 — Domestic Chinese share in bonding and sub-0.5um overlay metrology is near zero, which is the premise that makes the control bite. This measurement had

China is choosing the vertical escape specifically because it is litho-constrained and NOT bonding-constrained

43% if the 3 gates are independent, 60% if they move together. They are claims about one industry, so the truth is between and nobody can say where. Treat this as an ordering device rather than a calibrated probability — the ranking of premises is the information, not the level.

Weakest link: ChangXin Memory Technologies at 0.60 — Reported to be EVALUATING W2W hybrid bonding for bonded DRAM — separating storage cells from control logic. Evaluation, not a committed roadmap; grade

Therefore the incremental WFE dollar migrates toward a category where Chinese domestic share is near zero — and that is NOT where

69% if the 3 gates are independent, 85% if they move together. They are claims about one industry, so the truth is between and nobody can say where. Treat this as an ordering device rather than a calibrated probability — the ranking of premises is the information, not the level.

Weakest link: NAURA Technology Group at 0.85 — The consensus expression of the substitution trade, positioned in etch/deposition/clean — deliberately NOT wired to lithography or to bonding.

The variant

Consensus

Export controls cap Chinese advanced logic at the lithography step. Domestic substitution therefore accrues to the process steps China can already serve — etch, deposition, clean, thermal — which is why NAURA and AMEC carry the indigenization trade and why 'China memory capex' is expressed through those names. Litho is the wall; everything else is downstream of when China gets a scanner.

Variant

Litho is a wall only if the objective is smaller transistors. It is not a wall if the objective is more bytes closer to the logic, which is what the workloads actually demand. Four independent Chinese efforts converged on vertical integration inside one week — Huawei LogicFolding at 1.5um bond pitch shipping in Kirin 2026, DFSX stacking 3D DRAM directly on 14nm logic with no microbumps, CXMT evaluating W2W bonding for bonded DRAM, and the tau-scaling roadmap that frames all three. A domestic 14nm logic wafer plus a domestic DRAM wafer plus hybrid bonding is a complete AI accelerator that requires no controlled tool at the litho step. If that is the route, the binding constraint migrates to bonding and bonding metrology — where domestic presence is near zero, volume requirement rises sharply, and the trade is NOT priced.

Differentiator

The market is pricing the substitution trade in the category where substitution has already happened. NAURA's share in etch and deposition is the consensus expression and is largely in the price; mandated orders at mandated prices show up as revenue growth with margin compression, so the upside there is capped by the mechanism that creates it. Bonding is the category where localisation is near zero AND the volume requirement is about to rise — the only combination that produces a re-rating rather than a revenue line. The desk holds the mechanism as GEOMETRY (perimeter-area-scaling-gap: compute scales with area, I/O with perimeter) rather than as vendor advocacy, which is why it survives stripping out the Huawei source.

Falsifiers

claim: A credible domestic W2W hybrid bonder qualifies at volume · criterion: Any Chinese vendor (SiCarrier, or a new entrant) publicly qualified for production wafer-to-wafer hybrid bonding at sub-2um pitch at CXMT, SMIC or YMTC, evidenced by a customer disclosure or a teardown — not an announcement · horizon: 2028-06-30 · settles: refuted
claim: The vertical route does not materialise · criterion: DF2000 fails to ship in volume by end-2027, AND CXMT ships no bonded-DRAM product, AND Huawei's Ascend LogicFolding date slips beyond 2031. All three, because any one of them carrying the route is enough · horizon: 2027-12-31 · settles: refuted
claim: Bonding demand shows up in the incumbents' order books · criterion: BESI plus ASMPT combined hybrid-bonding-attributed revenue grows faster than NAURA's total revenue over any four consecutive quarters through 2028 · horizon: 2028-12-31 · settles: confirmed
claim: SCOPE — the trade is already priced · criterion: BESI and ASMPT outperform NAURA over the horizon by less than the semis benchmark's own dispersion, while the vertical route demonstrably proceeds. The mechanism was right and produced no tradeable consequence · horizon: 2028-12-31 · settles: refuted

Open questions

W2W hybrid bonding has COMPOUND YIELD — a defect in either wafer kills the pair — which is why layer count is the number nobody discloses. If yield does not scale, the vertical route stalls and this thesis fails on execution rather than on economics.
The desk has NO figure for bonder units required per wafer-start under a bonded-DRAM flow. Without it the TAM shift is directional only, and the thesis cannot be sized.
SiCarrier is the live risk to the whole variant: a state-backed broad-line entrant appearing mid-cycle could close the bonding gap faster than a foreign-share thesis assumes. Its capability is asserted, not demonstrated — but it is the specific name that would refute this.
Thermal is unaddressed in every vertical design the desk has seen. DRAM retention degrades sharply with temperature, which is precisely why HBM sits BESIDE logic rather than on top of it.

Reasoning chain

The physical mechanism is real and vendor-independent: perimeter-bound resources cannot keep pace with area-scaled compute, so packages must go vertical VALID

premises

Perimeter-vs-area scaling gap (the N-squared vs N fan-out dilemma)0.90 strong
Asserted by Huawei, which needs litho-independent scaling to be true, AND demonstrated by NVIDIA's shipping roadmap, which has no such incentive.
why
Convergence from opposed incentives.
Hybrid Bonding0.95 strong
REACTIVE from derived:hybrid-bonding.demand_pull (today 56.4, band 22.56-90.25 -> p 0.8-0.98).
why
Demand pull on hybrid bonding is the direct read on whether the vertical escape route is being taken. It is the closest computable proxy the desk has for the thesis until domestic-bonder-share acquires a quantitative series. Anchors are centred on today's reading so this makes the premise LIVE without re-rating the thesis. In volume production today at TSMC (SoIC) and AMD (3D V-Cache). Not a forward claim.
Perimeter-vs-area scaling gap (the N-squared vs N fan-out dilemma) supplies Hybrid Bonding1.00 strong
The geometry argument's own resolution: move memory, power and I/O onto surfaces where they scale as area.
why
Bonding is how.

Compute scales with die AREA while memory bandwidth, I/O and power delivery attach at the EDGE and scale with perimeter. No transistor improvement closes a topological deficit. The escape is to put the perimeter-bound resources on a surface, which is what bonding does.

China's vertical escape is now constrained at the SAME chokepoint this thesis identified, as of 2026-08-01 VALID

premises

Bonding Not Litho — signal 2026-08-010.80 strong
80%
Japan METI placed the complete back-end advanced-packaging chain under case-by-case licence effective 1 August 2026, hybrid bonders included, at a ~80% rejection rate for advanced-process applications, with original-manufacturer MAINTENANCE also ending after a one-month transition.
Chinese domestic share of wafer-to-wafer hybrid bonders0.75 strong
Domestic Chinese share in bonding and sub-0.5um overlay metrology is near zero, which is the premise that makes the control bite.
why
This measurement had been held and cited by NO premise until now; the export control is what makes it load-bearing.

The thesis identified bonding as the migrating chokepoint and Japan has now export-controlled exactly that category, first among back-end equipment, which is corroboration of the mechanism from a party spending political capital. But it INVERTS the China leg: conclusion 2 argues China chose the vertical route because it was not bonding-constrained, and after 1 August it is. The maintenance cutoff matters more than the procurement ban — new-machine restrictions slow expansion while ending vendor service degrades the INSTALLED BASE, and sub-0.5um overlay drifts out of spec in ways that are unrecoverable without the original manufacturer. HELD AT AND RATHER THAN OR because both must hold: the control must bite, and domestic share must stay near zero. The falsifier is a credible Chinese hybrid bonder at production overlay, which would make the control an accelerant for substitution rather than a block.

China is choosing the vertical escape specifically because it is litho-constrained and NOT bonding-constrained VALID

premises

Dongfang Suanxin (DFSX)0.75 strong
14 nm
Shanghai startup out of stealth 2026-07-13 stacking 3D DRAM on 14nm logic by wafer-level hybrid bonding with no microbumps.
why
Pre-production: DF2000 is Q4-2026. Real company, real funding, unproven manufacturing.
ChangXin Memory Technologies0.60 moderate
Reported to be EVALUATING W2W hybrid bonding for bonded DRAM — separating storage cells from control logic.
why
Evaluation, not a committed roadmap; graded accordingly.
US Export Controls on Advanced Semiconductors0.95 strong
The constraint that makes vertical the rational arbitrage.
why
Not in dispute.

Three separate Chinese actors reaching for vertical bonding within one week is a pattern, not a coincidence, and the common cause is that bonding is the one advanced-packaging step no export control currently gates.

Therefore the incremental WFE dollar migrates toward a category where Chinese domestic share is near zero — and that is NOT where the substitution trade is priced VALID

premises

BE Semiconductor Industries (Besi)0.90 strong
Hybrid-bonding incumbent, already wired as an enabler of hybrid-bonding in the graph.
NAURA Technology Group0.85 strong
The consensus expression of the substitution trade, positioned in etch/deposition/clean — deliberately NOT wired to lithography or to bonding.
Etch (plasma etch)0.90 strong
The step China is closest to solving, which is exactly why the trade there is priced.

Realistic domestic content in a Chinese memory fab is ~15-25%, concentrated in etch, deposition, thermal and clean. Bonding and sub-0.5um overlay metrology sit outside that band. If vertical integration is the route, the volume requirement rises fastest in the category with the LOWEST localisation — which is the opposite of how the trade is currently expressed.

Sources

Huawei LogicFolding: 1.5um bond pitch in Kirin 2026, gear ratio target below 3, sub-0.5um overlay, sub-1.5um TSV CD/KOZ — link acc 2026-08-03
DFSX 3D near-memory compute on 14nm, wafer-level hybrid bonding without microbumps, DF2000 Q4 2026 — link acc 2026-08-03

Write-up

Pre-filled skeleton: bonding-not-litho.md